Hardware Verification Engineering

Hardware Verification deals with development of methodologies, algorithms and tools for the formal and semi-formal verification of hardware and embedded systems.

Pacific West’s ESL verification

Pacific West’s solution for enterprise system-level (ESL) verification, combines automated hardware, embedded software and system-level verification with system-wide management and new high-performance engines. This solution, combined with our incisive Plan-to-Closure Methodology, extends the traditional electronic system level approaches focused only on systems engineers and C-level tools to the rest of the enterprise with a path from an executable plan to system-level closure.

Pacific West's solution enforces the system requirements across all engineering functions doing design and verification from an abstract system-level model and verification plan to in-system IP verification, systems integration, validation and closure. The result is predictable system-level quality and 50% reduction in time to market for complex system-on-chip (SOC) designs for consumer, networking and wireless electronics markets where significant amounts of embedded software are part of the design and verifying hardware/software interactions are a major issue.

The solution comprises three new system-level innovations spanning the full enterprise:

• Automated hardware, embedded software and system-level verification applies proven techniques from advanced hardware verification to embedded software and system-level verification.
• System-wide management extends proven hardware plan and metric-driven verification management to embedded software and system-level verification.
• High-performance engines - enable new higher performance emulation and System C simulation models to be accessed from system-wide management and the hardware/software automation environment.

As the industry moves toward 45-nanometer technology, we are seeing significant product life cycle cost and profit challenges for advanced SOCs. These system-level complexities will continue to increase the demand for enterprise-wide verification solutions that link together the hardware, software and system integration with the validation process

Pacific West's approach of applying efficient hardware verification techniques at the system-level, as well as offering verification solutions at each step of the design phase can decrease development times and costs in addition to reducing the need for re-spins.

Pacific West’s solution provides mechanisms to allow a unified verification environment to control and monitor both hardware and embedded software simultaneously, allowing multi-specialists to target these cross boundary issues with well-proven advanced verification techniques.

Since the design complexity has drastically increased, verification at different stages of ASIC development has become absolutely essential. Various techniques and tools have evolved to support verification. There are different types of verification depending on the development stage:

• Functional verification
• Assertion-based verification
• Formal verification
• Gate-level verification
• Wafer testing
• Chip bring-up verification
• Manufacturing verification

Functional verification

Functional verification determines correctness of logic in design before it is implemented on a device. It is used to check design compliance with specifications. Functional verification takes place during the early stages of the design flow so as to detect design flaws early in the chip development process. With the ever increasing complexities and an increasing use of reusable IP blocks, each new system IC and IP core has to be verified to eliminate discrepancies between the design and its specifications to ensure that the manufactured device functions properly. The test environment is developed and designed as per specifications. It generates and drives the defined stimulus to DUT (Device Under Test). Because timing information for the implemented design is not available, simulation tests the logic in the design using unit delays. Following are methods of carrying out functional verification.

Conventional Verification

Conventional verification is a BFM-based (bus functional model) approach where test benches are HDL (Verilog/VHDL) or 'C'-based. The verification engineer using this approach targets one bug/scenario at a time. Here, verification is restricted by the verification approach and the verification engineer's visibility of the test scenarios. But, attaining mere code coverage is no longer sufficient. Directed test cases have lost relevance now that designs have become very complex and SoCs have millions of gates. They are written only to fill remnants. And there aren't enough hits with a single test run. Thousands of iterations are required for full functional and code coverage. The major drawbacks of HDL-based verification are:

• Test cases, as opposed to coveraged, are defined.
• Absence of random environment and random test case generation required to fill maximum coverage.

Hardware verification language (HVL) based verification

Randomization, coverage, and analysis-based environments are implemented using HVL-based verification. It decreases the time and effort to verify and increases the verification strength. Only coverage groups need to be defined and the compliance checklist mapped in them. Using HVLs, the verification engineer is able to:

• Implement checkers, sequences.
• Generate signals, temporals.
• Inject and generate error/invalid scenarios and illegal conditions.

HVLs support use of coverage-driven verification methodology that enables complete verification of DUT using automatically generated real world scenarios. They also help create an integrated verification environment that supports constrained random traffic generation and functional coverage. This increases test range significantly and enhances maximum possibility for all kinds of corner cases. Automatic generation of transactions implies automatic coverage of corner cases and real world scenarios.

Benefits of HVL-based verification:

• Automatic, Random and Constrained Random generation
• Automatic generation of transactions possible.
• Automatic coverage of corner case scenarios and unknown corner cases.
• Random packet generation and transmission resulting in greater possibility of hitting unexpected cases.
• Random and constrained random generation supported.
• Ranges, rules on generation possible for directed random packet generation.
• Unknown corner cases covered .
• Coverage Driven Verification
• Automated random generation functionality coverage.
• Measure of verification completeness provided by functional coverage.
• Corner cases exercised, with addition of a few directed test cases.

Pacific West Verification Engineer’s specific capabilities:

Pacific West’s Verification Engineers handle hardware verification tasks required for client's products. Our Platform Integration and Verification (PInV) engineers would perform tasks associated with old style functional tests with state of the art verification techniques. Our Engineers would conduct hardware design reviews and support EMC, Product Safety, NEBS and various other related test efforts. Apart from which, Pacific West’s Engineers perform System Level, Module Level and Component Level Hardware Verification of Hardware Platforms. They also perform basic Form, Fit and Function related verification efforts, PICMG Compliance to ATCA, MicroTCA and AMC standards. Our Engineers create test cases/procedures and maintain incidents database to support client’s Engineers. Our Engineers leverage UML’s capabilities to efficiently and effectively complete design and design review related tasks. UML Modeling tools enable users to improve communication by specifying, visualizing and documenting their system and software designs using a standard graphical language. Also allows users to gain access to a robust graphical design environment to increase their productivity and shorten design cycles.